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I've have a question about PlaceDesign. When I'm using timingdriven within a constraints. I suppose that FE should do STA before doing placement. So 've just wonder how the delay (nets, cell) are calculated, because FE don't have informations about the routing (load+capacitance) and input transitions.So my question is:- Which setUseDefaultDelayLimit has been used (default > 1000 fanout)?- Which setDefaultNetDelay has been used (default 1ns by > 1000 fanout)?- Which setDefaultNetLoad has been used (default 0.5 pF by > 1000 fanout)?- What does FE with pre-specified clocktree before placement?- And which critical paths should FE try to optimize first (the worst paths)?. (FE could start to optimize on the worst paths which should be from a reset signal with a very large number of fanout but the timing is not a issue)Regards,
Hi DN,I have some idea on how it is done; but it is base on my understanding of the methodology, and so might be incorrect. Here it goes:- Pre-specified clock tree is for the tool to recognise the clock gating cell. Placement of the clock gating cell is as important as the placement of the FF. This will result in a better clock tree- At the end of the day, global placement is mainly congestion driven + optimise the wire length. Timing coming in as timing driven, but I think it is mostly an iterative improvement at the later stage of global placement.- Cadence has a new approach call "virtual buffer tree" which you can see in the log file at the beginning of placeDesign. It will buffer the HFO, and thus signal like reset tree is not so bad as it is seen after placeDesign.Personally, I prefer placeDesign to perform some type of sizing and buffering. By not doing so, it cannot more accurately identify critical path during global placment. As a result, it is more common to use region/fence for SOC (okay, it is my limited experience and may be very biased. Do correct me if you think otherwise).Regards,Eng Han