Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
The standard cell I am using does not have substrate and n-well tap, so
I have to placed well tape cell at regular interval in the core.
My perference is to use place them in checkerboard fashion. But I am
hit with what I believe is a limitation in the command addWellTap. It
is not easy to explain, so please be patience.
Let assume the max distance between the well tape is 40um (to simplify,
we ignore the width of the well tap and the height of the cell row). So
the command to add well tap should be:
addWellTap -cell wellTap -cellInterval 160 -checkBoard
The cell interal is 160um because a well tap can cover 40um on both
side. Also, in between the two cell taps on the same row, there are two
well tapes on the upper and lower row which are exactly in the middle.
Hence the spacing is 160um. The following drawing explain this:
(Note: X is the tie cell)
The problem occur when the upper or lower row is not available to place
the well tap cell (e.g. due to macro or placement blockage). In this
case, the tool shold place the well tie cell 160/4 or a max of 40um
away from the edge of the row. The tool now place it 160/2 or 80um
away. This is incorrect from my application of the command:
... Macro ... X
The distance marked "!" above is less than 160/2, but larger than 160/4. So an DRC will occur here.
Is there a workaround or hidden switch to get this command to work? Thanks.
Hello Friend ,How about using the below options -fixedGap with addWellTap :If not can you move your Macrocells accodingly to align .ExamplesThe following command preplaces a well-tap cell xyz on every row in the floorplan, with the distance between two consecutive cells not exceeding 40 µm.addWellTap -cell xyz -prefix welltap -maxGap 160 -fixedGap 40And you can add option : -fixedGapFYI.-fixedGap Ensures that the specified gap is always maintained. That is, this will not search for a legal location if it cannot place well-tap cells at the given -maxGap. Instead, it goes on to place well-tap cells at the next position. -maxGap microns Specifies the distance, in micrometers, from the right edge of one well-tap to the left edge of the following well-tap in the same row. If well-tap cells cannot be placed at this gap due to placement blockage, placement will search for a legal location: first towards the previous well-tap, and then away from the specified location. Under no circumstances can the gap between well-taps be less than 45% of the specified maxGap value plus the well-tap width. The distance is measured from the center of the cells.
Hi Mohan,It is not easy to shift the macro as the design has more than 100 macro of different sizes.The option "-fixedGap" does not take an argument. So we can only either say "-maxGap 160" or "-cellInterval 160". The issue is that the tool will always take 160/2 as the maximum allowable distance. This is not true for checkerboard style.More info on where the issue can happened:1. Between the left side of the core to the left side of a macro (a small area for buffering and JTAG cell)2. Between the right side of a macro to the right side of the core (a small area for buffering and JTAG cell)3. on the left and right side of the macro4. A single row betweent two macros (at the right side of these rows)Regards,Eng Han