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I am working on hierarchical design.I want to do a hierarchical bottom up CTS.At partition level, after CTS, I want to allign the external clocks (The clocks related to input/output delay) with my internal clock to continue the flow.I need first to characterise my internal postCTS clock network latency.I need to focus on my boundary flop, I am dealing with useful skew for internal flops...How can I get this clock latency information only based on boundary flops ?Is it possible to get the list of boundary flops ?Any other ideas ?Pat.
Dear bougantp:1. You can write a FE-TCL script to do this. 1st to get all the ports of your hierarchical block, the trace from this port & get all the registers, this is what you want!2. You can report the in2reg & reg2out timing, then use some PERL or VI to achieve this. Seems not easy.FYI
It is quiet easy to get the list of ports, but how can I do to get the associated flops ?
If you use the timeDesign command it will create timing reports with in2reg and reg2out (Don't forget to set your -numpaths high enough). From there just grab the subsequent Endpoint and Beginning to get the register names. To get more expanded information use the report_timing command with the "-path_type full_clock" option to include the clock tree. You can also use report_timing to do the first step, depending on your block size, it may be faster to time each port individually and then grep the report.
Design size is quiet big : 1200Kinstances, and number of ports is in the range of 4K to 7K, so a script based on foreach port get report timing ... might be very long (?)..
pls use dbForEachCellPort command to loop all the ports of your top cell, then get the port name and report timing according to the port directions, use report_timing -from or -to, then get all the FFs. Thre must be a ENDPOIT, I think this ENDPOINT is waht you want. Thanls jaredlee, you give me a idea, easy than a full TCL code.