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I am trying to create the power routes using Encounter 9.1
There are lot of memories in the design which has power pins in layer M4 ( design is 8 Metal layer process) i create the stripe in M3 & M7 where in M7 gets tapped to some of the power pins of the memories as the pitch of M7 is such that some of the memory pins does not get over lapped with M7 stripe so those are left open. so i create a sub mesh kind of struture on those memory pins & connect the sub mesh to the stripe in M7
During this stage there are lot of Stacked Via Violations are created,
Can i use any switchs or any settings so that the tool understands the requriment & create the stack vias properlly.
It's hard to say without knowing the specific via stacking rules for your process. Usually, power vias do not trigger via stack violations because the metal is wider and via arrays are used, instead of a single via. Most via stack rules only apply to single vias - arrays do not trigger the violation. Are your power stripes thin enough that you only have one via cut at the intersections? There are some different via stacking keywords available in the LEF file that may help you, but I'm not sure what your paricular violation is. What is flagging the violations? VerifyGeometry, or your signoff DRC tool?
In reply to Kari:
In reply to deeps:
Can you paste the exact wording of the verifyGeometry violation along with a picture of the violation?
I am also seeing below issue ,
Regular Via of Net design1/mlm_ahb_main_i/FE_OFN86065_sram_main_wdata_298_ & Regular Via of Net design1/mlm_ahb_main_i/FE_OFN86065_sram_main_wdata_298_|( VIA5 VIA1 )bbox = (2312.905, 1807.365) (2312.975, 1807.435)
In reply to noorcadence:
What kind of violation is this? Short? Spacing? A picture would help...