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Hi,In the Floorplaning we will place macros manually according to logiacal connectivity. If we have suppose 24 macros and i have placed these macros in the four (4) rows an 6 colums.1. How to specify the distance between 2 macros for all sides(top,left,bottom,right) and what r parameters to be comsidered?2. Any good document which specifies the designing the power structure or how to design the power structure? what are facors or parameters are rquired to design power structure(designing power strap widths, number fo power straps)?3. In IR drop analysis, how switching factor, probability and toggle rate works (means how it works in the process or IR drop implimentation)?Please suggest me Thanks & Regards,Prashant
Hi Prashant,For spacing/aligning your macros, check out the floorplanning options:Floorplan->Edit Floorplan->Align Instances, Shift Instances, Space InstancesThe power question is a bit more difficult to answer. Coming up with a power grid can be challenging. You want to have a grid that supplies enough power to all your components without going below an IR-drop limit that you have decided on. Most folks pick 5% of the supply (that means a 2.5% drop for VDD and a 2.5% bounce for VSS). Then you need to decide which layers to use for the grid and the widths. Most people do back-of-the-envelope calculations or use a spreadsheet which calculates the IR-drop based on total power consumption, supply voltage, resistance of the metal layers, and widths/pitches of the metal layers. You can plug different widths and pitches for the layers into the spreadsheet until you get an acceptable IR-drop number. This can work well for wirebond designs, but becomes much more complicated for flip-chip designs. (But flip chips will need less of a grid, since power is coming into the design at regular intervals and not just from the chip boundary.)You will also want to center your power stripes on the routing grids so that you don't use up signal routing tracks unnecessarily. We have also found that more stripes of narrower width are better than fewer stripes of wider width for routability. But you don't want the power stripes to be too narrow (too much resistance). It's a good idea to do IR-drop analysis as early as possible in the flow to vet your power structure. When using a toggle rate for IR-drop analysis, a typical number is 20%. Some folks think this is a bit high, but others will say it's a bit low. It really depends on the chip and how it operates. For example, in test mode, you may be toggling everything more than you would in functional mode, and may want to use a higher toggle rate. But in general, the clocks use the most power and they are always toggling 100% (except for gated clocks).I probably didn't completely answer your power questions, but as you can see, there is a lot involved.I hope this helps out at least a little bit.- Kari
Prashant,I forgot to mention that you might try the Synthesize Power Plan feature:Power->Power Planning->Synthesize Power PlanYou enter the total power and desired drop and Encounter will create a starting power plan. You can use this as a guide to get started and refine it from there. I have not used this before, so I don't know much more about it.If you are using planDesign for floorplanning, you can also take advantage of the Automatic Power Planning feature associated with that. (This is in SOCE 6.2 - I don't know which version you use.)- Kari
Thanks kari!I was using older version of SOCE-4.2. Regards,Prashant
You're welcome, Prashant. The shift/align/space commands are available in 4.2, although they might be in a slightly different menu location. But I'm pretty sure that APP and planDesign were not around back then.- Kari