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Hi!right now, I am working on a project using SoCE4.2. The library I am using contains these kinds of clock buffers, which are all output complementary, Q and -Q. Unfortunately, while I specified them in my *.ctstch file and ran the CTS, the errors appeared:
ckSynthesis Option : -rguide digital_cts/digital_cts.guide -report digital_cts/digital_cts.ctsrpt **WARN: cell CK01D1 has more than one timing arc. Check the timing libraries.**ERROR: Buffer CK01D1 specified in the clock tree specification file is invalid.Usage: ckSynthesis [-clk ] [-report ] [-rguide ] [-macromodel ] [-check] [-forceReconvergent] [-dontFixAddedBuffers] [-breakLoop | -ignoreLoopDetect] [-addOriginalNet]**ERROR: ERROR: Incorrect usage for command "ckSynthesis".
So I have to use those simple normal buffers & inverter instead. Although this time the CTS succeed, I am not quite satisfied with the CTS result report, cause the discrepancy between the rising skew and falling skew is huge:
Rise Skew : 506.3(ps) Fall Skew : 1358.5(ps)
I guess this is due to the performance of the simple buffer & inverter is not as good as the clock buffer.So I wanna try to use the clock buffer back in the CTS. Can anybody tell me how to fix this cell-CK01D1-has-more-than-one-timing arc problem?
Thanks in Advance!
Hi Gordonlyn,I think this is fixed in more recent versions of the tool. If you can't use a more recent version, you may be able to get away with a set_disable_timing on the unused arc (I'm guessing the -Q). As for the normal buf/inv tree, you could try using all inverters and see if you get something more balanced, but it's hard to say without knowing the details of your library. - Kari
Hi Gordonlyn,Unfortunately, I dont think CTS is able to build a tree using multiple output timing arcs cells. To handle that, it needs to figure out if it should build a tree after the Q or -Q output or both. Using inverters shouldhelp to reduce the difference between rise and fall skew because usually inverters have symmetric rise and fall time characterisitc or the tool can insert pairs of them to compensate the effect.Nevertheelss, it also depends on the gated clock structure that the designhas. If the clock has to go thru multiple of gating cells or muxes which has non-symmetrical rise and fall time,even if you have a symmetrical clock buffers, you may still get a difference of rise and fall skew. You may want to do a displayClockTreeMinMaxPaths -pin xxx/CK to see the details of the timing. (latest 4.2 should havethis cmd or try 5.2)
Thanks for your helps, Kari and bsg. I tried the method you've recommended - to use the inverters only in my CTS, and it works! After several times of trial-and-error, I got my results finally: Rise Skew : 331.4(ps) Fall Skew : 420(ps) Max. Rise Buffer Tran : 464.6(ps) Max. Fall Buffer Tran : 470.7(ps) Max. Rise Sink Tran : 442.6(ps) Max. Fall Sink Tran : 468.9(ps) Min. Rise Buffer Tran : 6(ps) Min. Fall Buffer Tran : 6(ps) Min. Rise Sink Tran : 120.1(ps) Min. Fall Sink Tran : 104.9(ps) Pretty symmetrical comparing with my previous one. :)While I was working on the clock buffer problem, writing the set_disable_timing scripts to disable the -Q timing arc in my *.sdc file, I still ended up with the same error. I just totally have no idea what to do. I think it might be better to make the clock buffer(Q) and inverter work together.
Hi all,Please can anybody tell me about how to calculate number of straps,power ring widths for a particular chip( if possible give some examples).And also give me the info about how to reduce the power dissipation while doing power planning in the physical design.I am waiting for the solution........