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can anyone plz tell me how can I extract physical gate positions on chip from its layout. I am very new 2 Cadence. So if very briefy u could plz write me how can i go from VHDL code 2 abstract layout (contains gate positions only).
If the chip is implemented flatten, you can try those:-- export a def file, (file->Export->DEF), then, from the def file, the "COMPONENTS" section will give you locations for all the instances.-- inside Virtuso layout editor, the "Edit->Search" will let you search instances by their name, and then, select them, and query their location.-- If you have Virtuoso VXL, you can do schematic--layout cross probe.If there are physical hierarchy, you have to look into individual layout view and convert their (x y) into top level when needed.Tongju
Thanks Tongju,I am sure this will be useful. I am working on SSTA implementation; and my tool needs to be feed with physical cell positions for timing analysis. Is it possible to genearate any file (netlist) which contains phyiscal gate locations and my scripts can then read this file for timing? I need to add automation to this timing flow so manual selection will not be feasible.Best regardsTouqeer
Does exporting a DEF file help? Another way is to write a skill program to print out the instance locations, like:cvid=geGetEditCellViewforeach(inst cvid~>instances printf("%s %L\n" inst~>name inst~>xy))Tongju
You can also try using dbInstLoc command.set instptr [dbGetInstByName ] dbInstLoc $instptr