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I am using Calibre-LVS for LVS check between final layout and verilog code both are generated by Cadence-Encounter v4.1. The output log file is enclosed.
The LVS does not compare two files because of some errors like:
Error: No matching ".SUBCKT" statement for "BFSVTX10" at line 43459 in file "/tmp/lvsRunDir/_decoder36.v.sp"
Error: No matching ".SUBCKT" statement for "BFSVTX10" at line 43460 in file "/tmp/lvsRunDir/_decoder36.v.sp"
BFSVTX10 is a standard lib given in STM cmos90nm lib.
I appreciate your comment to solve this issue.
Ali,I'm can't seem to download your log file, but first I assume you ran v2lvs to convert your verilog to spice, right? (Looks like it from the filename.) When you do this, you have to point to a list of the spice files for the std cells in your design (and rams, IOs, any IP, etc.) If this is the step you're missing, let me know and I can give you some more help with the syntax.- Kari
Hello Kari,Thanks for your reply.There is a verilog translator integrated into the Calibre-LVS. I entered a verilog file (for netlist ) and a layout (a GDS file was imported to vituoso layout) as two inputs for the LVS. Hence I didn't use v2lvs. But if it is not a safe method please let me know the correct syntax.Also I didn't mention the std cells. I think this is the step I missed. How should I introduced them to the design? at starting point of the LVS check I see some warnings like this: "Warning: no module declaration for module CTBUFLVTX12_0 first encountered in module decoder36"CTBUFLVTX12_0 is std buffer from cmos90nm library.decoder36 is my top cell name.Thanks,Ali
Ali,Sounds like you may be running LVS from a GUI, which I have no experience with. I've always done command-line. I think we normally see those warnings about the module declaration and they are ok, but the SUBCKT errors you got later is what makes me think you're missing the std cell spice. I'm not sure what GUI line this will match to, but my typical v2lvs command looks like this:v2lvs -v design.v -s library.spi -o design.source.spice > v2lvs.logThe file "library.spi" looks like this:.INCLUDE stdcell.cir.INCLUDE io.cir.INCLUDE ram.cirMaybe that will help you match it to the GUI option. Hope it helps!- Kari
Kari,Where could the cir files be located?are they supposed to be in the technology kit? I just see spi and cdl files which have .subckt syntax for all cells. these files are in: ../kits/cmos90nm/CORE90GPSVT_SNPS-AVT-CDS_2.2/physical/CORE90GPSVT.spi or CORE90GPSVT.cdlRegards,Ali
Yes, Ali - I should have mentioned the other formats, sorry! I'm not sure which one you should use, .spi or .cdl - both may work. I guess try the .spi files first.- Kari
Hi,It seems the error of .SUBCKT moved one level down and closer to transistor level.What command do you use after v2lvs? Should I modify the layout netlist to include std cells?In gui, I entered layout and spice netlist for a smaller module and I got following errors in the Transcript page:Error: No matching ".SUBCKT" statement for "PHVT" at line 34742 in file "/CMC/kits/cmos90nm/cmos090/CORE90GPHVT_SNPS-AVT-CDS_2.2/physical/CORE90GPHVT.spi"Error: No matching ".SUBCKT" statement for "PHVT" at line 34743 in file "/CMC/kits/cmos90nm/cmos090/CORE90GPHVT_SNPS-AVT-CDS_2.2/physical/CORE90GPHVT.spi"ERROR: Source could not be read.*** Calibre finished with Exit Code: 4 ***The following is a part of report file: OVERALL COMPARISON RESULTS # # INCORRECT # Error: Properties missing on instances in source.********************************************************************************** CELL SUMMARY********************************************************************************** Result Layout Source ----------- ----------- -------------- INCORRECT IVLVTX0H INCORRECT FD1QLVTX1 INCORRECT NR2ALVTX1 INCORRECT FD7QLVTX1 INCORRECT NR2LVTX0H INCORRECT AO2NLVTX1 INCORRECT BFHVTX2 INCORRECT BFSVTX2 INCORRECT CTBUFLVTX12_0 INCORRECT CTBUFLVTX6_0 INCORRECT MUX41HVTX1I appreciate your help,Ali
Hi Ali,I'm sorry you're still having problems. I'm afraid we've gone beyond my limited LVS debugging knowledge. :-( Do you have a Calibre AE or Calibre support that can help you?After v2lvs, I go right into calibre -lvs.- Kari
Just to update the post:The reason for this error is that the layout version of the design is not fully defined in the transistor level. It seems STMicroelectronic doesn't provide the real layout of the cells.That's why it fails the LVS.Solution: performing block-box LVS, which only checks gate level instead of transistor level.