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Can we use VDD and VSS in place of TIE-HI and TIE-LO cells as they are logically equal .
In reply to diablo:
Don't some vendors allow direct VDD/VSS connections?
I'm not a layout guy, so I'm not sure how this is handled electrically (diodes, caps, etc.) but I've seen it before. Maybe some vendors allow but risk the noise issue?
Whether this is appicable for 90nm and 130 nm also or we are using its for 65, 45 or 28nm only .
In reply to vedamrit:
In reply to tstark:
We ever had this kind of direct connection in our 0.18um chips.
How to make a TIE-HI or TIE-LO cells to drive constant 1-logic or constant 0-logic electrically?
To what terminals we will connect VDD/VSS nets ?
In reply to Ganga111AtFPS:
TIE-HI and TIE-lo cells are already tied to constant 1-logic and costant 0-logic respectively.
To connect gates that are driven to constant 1 or 0 to tie cells, in RTL compiler there is command
'insert_tiehilo_cells -hi TIEHI_A7TULL -lo TIELO_A7TULL -all -maxfanout 20 -verbose'
To have global net connectivity physically, in Encounter you will have to run