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1. I was interested in knowing how can we slot wide metal connects in our automated flow of encounter, I have found an option in place and route, its a guide file which is a text file but that is an option which is not viable.
2. How can I increase the width of the routing metals.
Thanks in advance
We recommend using wire groups during addRing and addStripe to avoid max width violations. See the options -use_wire_group, -use_wire_group_bits and -use_interleaving_wire_group for addRing and addStripe.
In reply to wally1:
Thanks Brian for the help... just a few more questions
1. How can we input the DRC file in Encounter so that encounter respects our rules while placing and routing.
2. I was looking at the Edit->wire->edit and it has a "wire group tab" , although I havent tried it yet but it did not seem to solve my slotting issues but the "misc" tab had some switches which seemed to be helpful, question being am I looking at the right place.
Thanks in advance.
In reply to BraveHeart:
The DRC rules are defined in the technology LEF file.
In regards to Wire Groups you can enable them during addRing, addStripe and Wire Editing. Attached is a short video (Shockwave) demonstrating their use.
Thanks allot for the useful information and the video. One other enquiry is that if we have a long wire and our DRC rules dont allow that how can we break the wire and insert a different metal in between. for e.g we have a wire length greater than 400 microns and our DRC rules dont allow that then we should insert jumpers in a different metal.
1. I think , correct me if I am wrong it can be done by including the DRC file in the tech file?
2. Is there any automated option where if the wire is exceeding a particular length the tool should break it and insert a different metal to reconnect the wire?
By "DRC file" do you mean the DRC deck? That cannot be read into Encounter. The technology LEF file defines the rules Place & Route must follow.
There isn't a rule in LEF to define maximum wire length per layer. I did some research and it seems the best way to minimize long routes on the same layer is to set the following during NanoRoute:
setNanoRouteMode -routeWithSiDriven true setNanoRouteMode -routeSiEffort high
The SI prevention will try to avoid long routes on the same layer.
Hope this helps,
Hope you are doing well, I am sending you a slide with questions in it.. Although i do understand the science behind the issues I am facing for example long metal wires have to be broken into pieces so that we have uniform spans after a number of grains to cater for charge accumulation, what I dont understand is how can Encounter help me to the fullest in overcoming these issues, There are a few Via issues that need to be addressed.
Thanks for all your help.
The flow for inserting multi-cut vias for signal routes using NanoRoute is described in this solution article:
For #2, can you clarify what you mean by "without physically connecting it to anything". Have you run SRoute to connect blocks, standard cells, IOs? addRing and addStripe are used to create the power mesh structure and SRoute is used to make the remaining connections. If you go through the tutorial below it demonstrates the flow:
Lastly, if their is a rule in your DRC deck not defined in the LEF you will need to define that rule in the LEF file. The LEF/DEF Reference Manual can be found in cdnshelp or on Cadence Online Support here:
You might check with your foundry to see if they have a technology LEF available to use.
thanks for the prompt reply, I am following the complete flow of encounter, By "Without physically connecting it to anything" I meant that I see multiple vias rather an array of 8 via's lying on the power rail but the via's are not connecting anything, they seem to be redundant, the question being why has encounter put them there if it did not want to connect any two layers.
Thanks for the links
i will spend some time over the weekend studying the links.
have a nice weekend.