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I've the following doubt in selecting clock inverters or clock buffers:
Q) on what basis we choose this much of high drive cells can be used to build clock tree?
is this design dependent like gate count of design and frequency of operation?
Generally I always prefer to use X8 and X12.Why can'n we use low drive like X4 etc..Is there any problem if i choose low drive cells?
Can any body give some clear explanation for the above question?
Large buffers near the CTS root to keep the intermediate input pins transition sharp on these long routes. Smaller buffers are more apropriate for shorter but high fannout leaf driver cells. "SinkMaxTran" & "BufMaxTran" are droping with each tech node 32nm < 100ps
Give CTS the full variety of buffers and inverters and see what it wants to naturally use.
In reply to fitz:
Thank u ftz for ur reply...
in cts to reduce latency we are adding buffers(parallel) i.e we have to add high drive strength buffers near clock root and we have to come in descending order of buffer drive strength from clock root to clock sink i.e x12 near root x4 near sink...this is because to reduce DELAY VARIATION between the buffers.....and to maintain cap value......
correct me if i m wrong
In reply to sathyarao:
yes you are correct to reduce latency we go for high drive cells like X12 to drive large fanout loads ....
But can we follow this concept(using of high drive cells) for every design even the design is working with low frequency??
obviously we have to use high drive cells for high frequency designs to get sharp transitions at clock pins ....
My question is on what parameter we chose this much drive cell is enough to drive clock tree??
I think u got my point...
In reply to Ganga111AtFPS:
Our vendor has strict technology node dependant SinkMaxTran & BufMaxTran rules.The early / late clock derating factors used to calculate On Chip Variation are characterized within these input transition boundaries.Break the clock input transition rules and your STA timing margins may not be valid. ( not a warm fuzzy feeling at tapeout )
We always add a good bit of clock uncertainty in our constraints to add extra margin on top of OCV derating. That way if we are just barely meeting timing, we know we still have a good bit of margin built in.
In reply to Scrivner:
At every stage while building delay tables ,cap_tables and giving uncertianity for a design the vendors and designers like us taking margins..
so that even we met barely in STA not a problem for tape_out..