I cannot use RootInputTran in the clock spec file to
specify the input transition at the clock root since the clock is not specified at an input pin/port.
The clock report shows that CTS used the default root input tran value of 1ps which is way to fast for this design (periods for clocks 47ns and 100ns).
I recall seeing something about a setting/variable to tell CTS to take the driving cell into account to avoid using the default, but I cannot locate it in the docs or through online search.
Any suggestions ?
Does this do what you want?
set_global timing_clock_source_use_driving_cell true