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I'm working on a design that's giving me some trouble. The IO is different than any design I've done before. I need some of the IOs to be routed to traditional pads on the edge of the chip, and some of the IO routed to flip chip bumps. To help with the troubleshooting, I have created a new verilog netlist with only the AREAIO pad driver, driven by primary inputs, and outputs to a single bump. Up until recently, when I executed the fcroute command, Encounter would hang after giving a cryptic, repeated warning about "too many geometries". However, since then, I have changed something (no idea what) and that seems to have stopped, and I can't even force it. So, I apologize for the incomplete information. Now, the command completes successfully with no warnings or errors, but it refuses to route the signal. In the terminal, it shows a message of "Number RDL connection routed: 0 open: 1". In the Encounter window, there is a white 'X' on both ends of the would-be connection. When I open the Violation Browser, it simply shows two errors that are "Other > Connectivity > Open" with no explaination of why it could not make the connection.
I really do not know what steps to take next; all documentation I have been able to find supports my method, and I have no warnings or errors to investigate. I'm sure the information I have provided is incomplete for a solution, but I do not know what all is needed. I appreciate any help you all can give, and I will gladly give any/all additional information required.
Thanks in advance!