Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I am using EDI 10.12.002 to implement a processor design. I have my own library of logic cells which I mix with certain sequential cells, buffers and inverters of a vendor library. The geometric aspects and characterization conditions for the custom library cells match that of vendor librar but there are some differences in that the vendor timing libs are produced using synopsys tools whereas I obtain my libs from ELC.
During the routing phase I get this warning:
#WARNING (NRDR-128) Can not do via swapping using command 'globalDetailRoute', use 'detailRoute' command instead . Will do normal detail routing if possible.#Using multithreading with 4 threads.#Worst slack with path group effect 340282346638528859811704183484516925440.000000
What does this indicate?
Additionally, the optimization phase of routing goes on for a really long time and runs for a couple of hours(It has been over two hours now and still going strong). The timing constraint is a very relaxed 30ns and up until the routing phase I get a slack of 18+ ns. I intentionally have a relaxed timing constraint as the custom library cells have small and limited drive strength. I have a few essentaildelay constraints on the input and out put portsof the design but nothing else.
Could the long run times indicate missing false path constraints and/or multi-cycle path constraints? Is there a way to ascertain this and get more information? I suspect that the long runtimes are due to missing/erroneous constraints because I also have a generous floorplan and the design starts out with about 20% density but is buffered up to about 75% density (the slack also falls to only about 0.18ns). What could be the possible reasons for such large discrepancies in the reported slack and is there any way to ensure that false/multi-cycle paths are accurately accounted for?
Any help is appreciated.
Routing in EDI consist fom to big parts - global routing and detail routing. Looks like this warning informs you that one part could not do via swapping and recomend you to use another part for this. Rasons of this behaviour coul be in you setup try to find somethig related in descriptions of folloeing encounter commands:
Long run issue could have different roots. Short library is in the list.
To check your concerns try to use "checkDesign" and "checkTimingLibrary" comands.
In reply to VKhlyupin:
Thanks for your response. The root cause of this issue lay in incorrectly set timing constraints during synthesis. Once I corrected those, the resulting SDC from RTL compiler passed the correct path constraints to Encounter. The message about the worst slack also disappeared.
Your points are well taken however.