Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
as the subject says,
is not able to find any clock nets:
" **WARN: (ENCSYC-1188): Cannot select clock net - could not find it."
Although, I ran CTS in advance:
ckSynthesis -forceReconvergent -rguide par_$Utilisation/ctgen/$Entity.guide -report par_$Utilisation/reports/$Entity.ctsrpt createClockTreeSpec -output par_$Utilisation/$Entity.ctstch\ -bufferList $CT_BUFFER specifyClockTree -file par_$Utilisation/$Entity.ctstch
createSaveDir par_$Utilisation/ctgen ckSynthesis -forceReconvergent -rguide par_$Utilisation/ctgen/$Entity.guide -report par_$Utilisation/reports/$Entity.ctsrpt saveClockNets -output par_$Utilisation/ctgen/$Entity.ctsntf saveNetlist par_$Utilisation/ctgen/$Entity.v savePlace par_$Utilisation/ctgen/$Entity.place
I would be glad about any hints what to do.
It sounds like the clock net markings are getting purged from the database somehow. Try triaging it by querying the "isCTSClock" attribute on all the nets in the design after each step in your flow to see where they're getting removed:
encounter 11> dbGet top.nets.isCTSClock 1 1 1 0 0 0
I think you'll find that either tracing is malfunctioning somehow -or- some downstream command you're using before selectNet is purging the markings. Let us know if you find the problem and we'll get it repaired!
Hope this helps,Bob
In reply to Robert Dwyer:
thanks for your reply.I think the clock tree specification is not right because when I try to build the clock tree using
ckSynthesis -forceReconvergent -clk clk -rguide par_0.5/ctgen/entity.guide -report par_0.5/reports/entity.ctsrpt
I get the following error:
**ERROR: (ENCCK-725): The BufMaxTran 0.3 (ps) in the clock tree specification file for AutoCTSRootPin clk is too small to synthesize any valid clock.
Which value do I have to use for "BufMaxTran" ? I am not sure what this variable means.
My netlist was synthesized with 100 ns.
In reply to marten:
BufMaxTran is the target transition time you're asking the tool to achieve on buffers in the clock tree. You probably don't want 0.3ps. You probably want 0.3ns. Try supply the units (ns) in your clock tree spec file where 0.3 is specified for BufMaxTran. If you're not specifying this value and it's defaulting to that try specifying it to 0.3ns.
Hope this helps,Bob
Thanks Bob, it is working now!