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I need a clarification for the below issue. I have a 550k+ sinks for clk_sys. To get, better skew & insertion delay values. I found out the clock gating cells & mentioned those output as "AutoCTSRootPin" lets take CLK_GATE as clock name & has some 400k+. I mentioned those in the intial portion of the ctstch file and later my main clk "clk_sys" comes up. so, it will build for "CLK_GATE" 1st then it comes to clk_sys.
As the result, am getting better skew & insertion for CLK_GATE But for "clk_sys" am getting worst values. My question is, once clock tree is built for "CLK_GATE". when it comes to clk_sys tree. Whether it will re-build "CLK_GATE" tree again?
Hope my quesion is clear. Plz let me know any more brief explanation needed.
From the above question , I may say that u are assigning 400k+ sinks are driven by CLOCK_GATE , which mean only part of those 400k+ sinks are actually driven by ICG cells and remaining are driven as usual ( mean, without gating).
We can say that some of the sinks are actually not taken into consideration for calculating the skew, hence its resulting a better skew number.
Well to my knowledge there were 150k+ sinks are available which were not driven by clock gating and hence their skew became worse.
The clock which is specified in the ctstch file will be routed first. Hence CLK_GATE will not be built again.