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We have silicon/design that is strugling to recover from IR drop issue. To reduce the IR drop problem, decap cells are placed in design. My assumption is that decap cells reduce the impact of IR drop by supplying the dynamic current when there is a drop in voltage.
Our designs / patterns have IR drop issue that do not last more than 3 clock pulse of design. Due to the way logic is design, we are interested in only specific 3 clock cycles of complete test in which critical events occur. Rise edge of first cycle has high IR drop, which is recovered by decaps before second clock edge. Second edge has further IR drop but since decaps are already drained in recovering the IR drop impact of first clock edge third edge even more worst causing some paths to fail.
Between second and third clock edge, decap itself puts load on grid so that it can charge itself. This also impacts the voltage level of rest of design.
Bottomline is I have it is a sequential depth of 3 pattern which consuming power constantly. First two clock pulses all paths meet timing on silicon and passes and but fails on third clock edge.
Between second and third capture i have very less number of paths that I care about and should work, rest I dont care even if they are impacted by IR drop and become slow.
My question was, is there a way to protect a specific logic / path that should have least impact on IR drop in 2-3 cycle. What are the possible solutions for this problem.