Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Hi Even same problem i am facing thay dont have compatible version for VR_AHB 9.2 with respect to VR_AHB_TLM.and also they are not giving any kind of support on that.
In reply to abhineet22:
I think there's maybe a little confusion here. The Functional Verification Kit (KITSOCV) that ships with Incisive has a basic AHB UVC, which is really meant as an educational tool as part of the kit workshops. The fully featured AHB verification component with full protocol coverage (including AXI4 and ACE) is part of the VIPP92 and VIPCAT112 products on the download server.
VIPP92 is an old product to be used with Incisive 9.2 and 10.2, VIPCAT112 is the replacement product that works with Incisive 10.2 onwards and features a new more flexible licensing model, as well as other new protocols.
Regarding TLM, it's not clear from your message what feature you are looking for. The AHB VIP does support TLM, but your requirements are too unclear to say whether the current TLM support matches what you need / want.
I would strongly encourage you to work with your local Cadence AE to learn more about what the vr_ahb VIP can do, and to get some help to set it up.
In reply to StephenH:
Let me give the clear picture.
1.We are doing co-verification of RTL with equivalent systemC implementation, which implies that we reuse the RTL DUT verification environment for the systemC DUT verification also. And for this reuse, the vr_ahb_tlm add on IS A MUST.
2.It is natural that RTL environment uses the latest version of eVCs - in this case it is vr_ahb 9.2.
3.For some IPs, the systemC verification environment customisation began when the eVC versions that were used were early ones - like vr_ahb 2.2 in this case, along with vr_ahb_tlm 1.0a1.
4. But the RTL development went ahead and so also the vr_ahb eVC moved to newer versions like 9.2 5. Now when we want to resume co-verification with systemC DUT, the vr_ahb_tlm 1.0a1 not being compatible to vr_ahb 9.2 IS DEFINITELY A SHOW STOPPER. Because by co-verification, we guarantee the customer that RTL and systemC implementations are equivalent (and we have a host of IPs lined up for this), and as proof of this they should have run the same tests on the same environment WITH THE SAME TOOL VERSIONS.
If we cannot have the vr_ahb_tlm upgraded with vr_ahb eVC, then specman coverification of RTL with systemC will come to a halt!!
we already contacted local cadence AE but till now no updates.