Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
i use define in my testcase,what i want to do is in the first loop i use the define maybe in one branch ,while on the second loop ,i want #undef the define that i defined before and into another branch,but it doesn't work......
codes are like this:
#ifdef AAAA then
#ifndef AAAA then
what really does the sentence means in reference "The effect is propagated to all files that are loaded after the#undef statement is encountered."?
does it means the #undef could not write in just one file ? or between two import e file ,we use #undef ? like the example supported in e_reference:
#define semaphore my_semaphore;import my_design.e;#undef semaphore;import external_code.e;
thank you for your reply......
defines are preprocessor directives. If you want control flow in your code, I would suggest using variables or AOP features (i.e. modifying method in when subtypes). The e language gives you many features, exactly for the flexibility you are looking for. Preprocessor directoves are very un-flexible, so they should be the last resort.
In reply to hannes:
thank you very much!