Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I'm new to using interfaces and would like to implement an interface that connects a master module to 2 other identical slave modules. The interface simply contains a 2 bit data bus that is driven by the master. I would like the interface to split the bus such that one slave is driven by the LSB and the other slave is driven by the MSB of the bus.
I believe the easiest way of doing this is to use modports - a master modport and a different modport for each slave. The interface code would then look something like this (modports are on single lines for compactness):
logic [1:0] data;
modport master (output data);
modport slave0 (input .data_bit(data));
modport slave1 (input .data_bit(data));
endinterface : data_bus_if
I'd imagine this scenario is quite common but Incisive doesn't appear to support modport expressions. How can I implement the interface so that it compiles with Incisive?
Hi Sean (?)
Although Cadence has occasionally had requests to support that style of modport expression, it's not been of of the more popular features and as such hasn't been implemented yet. If you care to file a support request for the same, we can get you added to the list of people officially requesting it, which can help us when planning which features to implement next.
The following adaptation of your code does work in Incisive. Eventually you'd be able to replace the separate sub-interfaces with modports, as per the examples in the LRM.
interface slave_if ( input data_bit );
slave_if slave0 (.data_bit(data));
slave_if slave1 (.data_bit(data));
In reply to StephenH:
Thanks for responding, your workaround seems a good solution, however, I'm having problems elaborating my example design when I use a generate statement to create the slave sub-interface instances.
My code for a slave is:
module slave (slave_sub_if port);
In my top level where I instantiate each slave, I've used the following code:
slave slave_inst0 (.port data_bus_if_inst.slave_gen.slave_sub_if_inst);
Incisive reports the following error during elaboration (highlighting the slave_sub_if_inst name):
ncelab: *E,CUIOAI (...etc): Illegal interface port connection through a generate or array instance
The block within my generate statement is named "slave_gen", which is the same as the block in your code.
How should I specify the name of my sub-interface instance to ensure that my design elaborates?
BTW, I should mention that my design elaborated when I simply instantiated 2 instances of my slave (without a generate statement).