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We are migrating to an irun based flow to simplifiy our compile/elab/sim flow, and have a slight issue.
We have a file design.v, containing module design. Depending on a define, this can either be a standard digital module, or a WREAL model.
i.e. Within the file
This issue is that irun uses the file extesion to infer the type of file, in this case, it does not work.
This is a non-trivial design, so I have multiple verilog, vhdl and vams files, and using the -ams is probably not an option.
Question is: Can anyone suggest a solution? Is there an command line option that I missed, which applies to a single file only?
In reply to tpylant:
Thanks for the ideas
1) This would solve the immediate issue. We are currently not using SV, but will be in future. However, I guess that we would not be mixing wreal and sv in the same file.
2) Extra marks for "thinking outside the box", but no thanks :-) I don't think this solution would make me very popular within the company.
3) I had thought of this, but we would then start losing irun advantages.
One more thought I had is to use a verilog pre-processor+Makefile to auto-generate design.vams from design.v
For now, I'll go with (1)
Thanks again for the feedback.