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I am try to creating eRM Wrapper for sv Environment. In that environment systemverilog tasks/function which is called from specman e methods. I have better knowledge in both Verification component. but i need how to interfere this both Verification component. if any body have an Idea about this. share your knowledge this will helpful for me to update
function void m(bit [`ADDR_SIZE-1:0] addr,bit [`DATA_SIZE-1:0] data);
$display("ADDR: %d",addr); $display("DATA: %d",data); $display("iam here"); endfunction
.......here, how can i call above systemverilog function ?....
Thanks & Bestregards,
I'm not sure if I fully understood your intentions... There is a simple way to call individual SV functions from e, but you can also wrap complete UVCs so that the e env can instantiate and control a UVM-SV sequencer, driving sequences and transactions from e. There are examples for both, supplied in the tool installation as part of the SoC Verification Kit.
For the UVC wrapping, the example files live under <incisive-install-dir>/kits/VerificationKit/soc_verification_lib/mixed_ex_lib/e_over_sv_class_lib/
You can find a self-paced workshop with labs here: <incisive-install-dir>/doc/kit_topics/uvm_mixed/e_over_sv/workshop/Integrating_SV_UVC_in_e.pdf
If however you just want to do a simple function call interface, take a look at "Using e Method Ports with SystemVerilog Functions and Tasks" in the cdnshelp tool. It's under the hierarchy:
Specman Functional Verification -> Specman Integrators Guide -> Integrating the e testbench with SystemVerilog
Hope this helps.
In reply to StephenH:
Hello Stephen, Thanks for your reply.
I got key Idea about calling systemverilog function thro' e wrapper from a cdnshelp &[Using e Method Ports with SystemVerilog Functions and Tasks].Thanks alot for ur help