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Hi all, I have in the design a signal which is defined: SIGNAL win_energy_array : std_energy_array; in the package defined: CONSTANT NUM_OF_FIRS :INTEGER := 5;CONSTANT ENRG_MAX_BIT :INTEGER := 10 ;TYPE std_energy_array IS ARRAY (NUM_OF_FIRS DOWNTO 1) OF STD_LOGIC_VECTOR(ENRG_MAX_BIT DOWNTO 0); I have imported the package and defined a program,I tried to use the type std_energy_array as an input signal type and I got the error: unknown identifier,so I tried to define: import pre_proc_lib::*;program fb_fullchip_tb( input logic[5:1] win_energy_array [10:0]; ); and tried to bind them:program bind_prog; bind PreProc fb_fullchip_tb fb_tb ( .win_energy_array(win_energy_array) ) I also tried the following:input logic[5:1] win_energy_array ;input logic[5:1] [10:0]win_energy_array ; But I always get the error:# ** Error: (vsim-3055) Type of connected VHDL signal is incompatible with Verilog port 'win_energy_array'. The other signals in the program are connected all right. How should I define my this signal? Thanks