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I am trying to annotate an SDF to my gate level synthesis netlist and I am seeing some strange behaviour.
When I annotate using just the netlist, cell_lib and sdf , everything works fine. However, when I try to annotate using the testbench and providing the full scope to the netlist within the verification environment (SCOPE=test_env.<scopetodigtop>.udig_top), I see thousands of
SDFNEP, SDFNET errors. The paths and timing checks which ncelab is complaining about definitely do exist in the cell_lib verilog, and the scope is definitely correct. I have tried modifying the scope just to make sure that it was correct and with anything apart from these settings the annotator complains that the scope is incorrect and refuses to proceed.
What am I missing and what is the best way to debug this ?
I have tried versions incisiv/11.10.011, incisiv/12.10.011 and incisiv/12.20.008
In reply to andymont:
I am also getting several SDFNEP errors. I could not add the library file. I am using ADE, simulator is ams. I tried adding the library in Simulations -> Options -> AMS options -> Main tab -> VERILOG library files -v section.
I get the warning: ncvlog: *W,LIBNOU: Library "/path_to_library/library.v" given but not used.
My overall setup: I have a synthesiszed netlist file and SDF file after synthesis. I imported the netlist through File -> Import -> Verilog. The schematic and symbol was automatically created from the netlist. I have a verilog AMS testbench in which I instantiate the digital top level, and use $sdf_annotate to use the SDF file. In the config file, I choose the schematic view for the digital top level.
Could someone help me why am I not able to add the library file?