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I've been using the IFV tool for quite sometime now and I notice that when I run FSM assertions under AFA, No deadlock assertions remain explored while the others pass easily. Is there anyway to improve this?
besides increasing the effort and partitioning the design there is not much you can do. Note that the FSM NoDeadlock check is a very complicated check that has to verify the FSM in context of all other state bits as well as excluding unfairness on all inputs.
There is a change in FSM NoDeadlock checks starting in 13.1 that will improve performance significantly, at the cost of failures due to unfair input behavior. I recommend to try that and share the experience.
In reply to JoergM:
Thanks for the immediate response.
I tried the same RTL with the 13th version. All these deadcode checks failed as Fail (Inf). What do you mean by unfair input behavior?
In reply to Buvna:
from the IFV "Whats New":
In this release, the deadlock state property has been enhanced to check that the FSM cannot take any transition to the same state under any possible input combination.
This deadlock state is supported by all engines and results in an improved performance.
For complete information, see the section titled, "FSM Checks" in Chapter 10 of the Formal Verifier User Guide.
What is implicitly explained here is the fact, that any input, that can control the outgoing transition of a FSM state, is now allowed to stall the FSM in 13.1, resulting in a noDeadlock failure. It is now required from the user to analyze and decide if that scenario is possible in the intended system context or not. If not, the user may add a fairness constraint like "eventually! !stable(<input>) and reduce unfairness manually.