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I met a problem in using verilog and vhdl:
1) I use verilog to make a testbench while the DUT all are made by VHDL
2) I want to initialize the lower level memories in DUT. I have tried to use $nc_mirror, but it seems useless.
So would you like to give me some suggestions on how to initial memories in VHDL designs through verilog testbench?
I think we can only do this sort of initializing [vhdl DUT,verilog testbench and vice-versa]by using $nc_force and $nc_release.You can try this.
Please correct me if I am wrong.
In reply to shalem7:
Thanks for your kindly reply. It works by using $nc_force.
BTW, how can I transfer a integer variable from verilog to VHDL?
As the code shows bellow:
tb_top is verilog module;
vhdl_top and bellows are vhdl module.
$nc_force("tb_top.vhdl_top:ocmem:memarry[i]" , #data[i]);
The ERROR message is:
expecting a integer index i.
In reply to victorhan:
I am not sure about the error.I did not inderstand the # in #data[i].
data[i] also needs to be in " ".
nc_force command has to be like this.
If your memarray is of size 5,each single bit
$nc_force("tb_top.vhdl_top:ocmem:memarry" , "10010"); //if it is a single bit.
The important thing is not about how to use #data[i].
It's how transfer a integer i from the top file in verilog to the inner module writen by VHDL.
At test bench top file which was written in verilog:
for (i=0, i < 4096, i=i+1) begin
The array mem_int is beneth vhdl designed module, so my question is how can I transfer
the integer i to VHDL designed module mem_int?
I believe the problem is that you are passing the index into the $nc_force command as a variable rather than a constant. The task is expecting a string with the name of a signal. It isn't going to parse that name and do variable substitution in it. You need to do that yourself.
Try something like this:
integer i; reg [72*8:1] targetname, srcname;initialfor (i=0, i < 4096, i=i+1) begin $swrite(targetname,"tb_top.arcsys:ocram:aram:now:mem_int[%0d]",i); $swrite(srcname,"#data[%0d]",i); // I'm not sure exactly what #data refers to, but we're not talking about that... $nv_force(targetname,srcname,"verbose");end
In reply to TAM1:
Thanks for your kindly reply.
I have tried the method that you told me.
But it's still useless, the variable i still can't be transfered from verilog top file to the deep VHDL.
I put together a small example and this code appears to work:
reg [7:0] data [31:0]; integer i; reg [72:1] destname; reg [7:0] dataval;
for ( i=0; i < 32; i=i+1 ) data[i] = i;
for ( i=0; i < 32; i=i+1 ) begin $swrite(destname,"s1:mem(%0d)",i); dataval = data[i]; $nc_deposit(destname,"#dataval"); end
You may want to use $nc_deposit rather than $nc_force if you want to later be able to write to the memory later from inside the VHDL model.