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Hello all. So I am in the process of simulating my layout extraction. I ran DRC which was successful.I ran LVS which returned a negative output (my schematic netlist and extracted netlist DO NOT MATCH);however, I continued with the simulation hoping to see if I can gain some info from the plots...
Here is my layout and the plot of the simulation of the extraction (sorry for the bad quality layout image).
Please help me debug this issue. What should I be looking for?
Fixed! It is kind of obvious where the problem is! If you can tell the nmos seems to be working properly (as seen in the wave forms). It is the pmos part that seems to be messed up, it is also apperent that the pmos is simply not doing anything or in other words; not functioning... Hmmmm, what may cause such an issue? THINK ABOUT IT!!!
I didn't have a voltage source for my pmos! : (
Sorry for the premature thread, next time I will give it more thought. I have 93 views as of this writing though, I bet you guys are also working on the same assignment I am... Good luck!