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I'm trying to get a SystemC / Verilog simulation to run and am getting the following error messages:
There is no information on any of the warning or error codes in Cadence help or on this site. Has anyone got more information in these or suggestions on how to resolve them?
ncelab: *W,CUSRCH: Resolved design unit 'BLAH' at 'U_BLAH' to 'work.BLAH:v' through a global search of all libraries.ncelab: *E,SCK109: complete binding failed: port is not bound to any interface: port 'tb.dut.signal_in' (sc_in)In file: sc_port.cpp:247In phase: end_of_elaboration.ncelab: *E,SCK940: Error in SystemC elaborationIn file: sc_cosim.cpp:1249In phase: end_of_elaboration.ncelab: Memory Usage - 31.4M program + 72.5M data = 103.9M total (Peak 104.6M)ncelab: CPU Usage - 0.1s system + 1.6s user = 1.6s total (2.2s, 74.7% cpu)ncsc_run: *E,TBELABF: ncelab returned non-zero exit statusmake: *** [comp_sc] Error 1
> nchelp ncelab sck109nchelp: 12.20-s028: (c) Copyright 1995-2014 Cadence Design Systems, Inc.ncelab/sck109 = Port binding resolution done at end of elaboration has failed. This can happen if: 1) A port is unbound. 2) A port is bound to more interfaces than the maximum specified. 3) A port declared with the SC_ALL_BOUND policy has less interfaces bound to it than the maximum specified. 4) A port is bound more than once to the same interface.
Ports in SystemC must be bound to at least 1 channel.
In reply to muffi:
Thanks. I've fixed the error which was causing the port binding problem but now get the following error:
ncsim: sc_cor_qt.cpp:161: virtual void sc_core::sc_cor_qt::stack_protect(bool): Assertion `ret == 0' failed.
The same code simulated in Modelsim doesn't give this error.
In reply to MJT45:
Please check your code to see if an sc_module is being instantiated as a global variable before sc_main
We may require more information to debug this. For that, can you send in a mail to email@example.com?