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Hi,How do you verify the connectivity at the top-level? How to make sure a user has not messed up a[m:n] with a[n:m]? Do you generally use simulation and toggle coverage to verify this or formal?Your insight will be appreciated.Regards,Sibil
Hi Sibil, Let's take an example:- Assume the top level module is called top- Assume top instantiates blocks 'A' and 'B'- Assume blocks 'A' and 'B' have inputs data_in[63:0] and data_out[63:0]- Assume at the top level data_out from block A should be connected to data_in of block B You could write an assertion that checks that "top.data_out[63:0] is equal to top.data_in[63:0]". If you feed this assertion to IFV it will either be trivially true of trivially false; runtime should be very quick (should be approximately equal to the time it takes to read the design into the tool). Regards,Amir