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I am planning to use System verilog - not System C - for writing a test for a SOC ASIC. I am looking at Cadence online documentation and I can find just ncverilog and systemc, not system verilog. This confuses me: I do not want to go that far with System C, so I like System Verilog which let me have a resonable learrning curve: I still have the ability to either design synthesizeable logic with verilog 2001 AND write mid-to-high level verification code in the system verilog without referring any object code - either SystemC or C++ - in the simulation model, just compiling everything.Question is: how do I compile Sytem verilog in a Cadenc e simulation environment? I acannot find the keywords 'system verilog' in the cdsdoc engine either ...many thanks in advance
SystemVerilog has been supported as part of ncverilog since IUS53. You will need to use the +sv (+sv31a before IUS56) command line option in order to have it recognize the SV keywords. You will need an Incisive license to run assertions or object oriented testbench constructs. However, all the design constructs will work with a standard NC-Verilog license.As for the documenation, there are four new manuals:- SVA Quick Reference- SystemVerilog DPI Engineering Notebook- SystemVerilog Reference- SystemVerilog: What's NewTim
Hello TImthanks for your reply.I getapollo stanzani:coyote > ncvlog -svncvlog: 05.10-s017: (c) Copyright 1995-2004 Cadence Design Systems, Inc.ncvlog: *F,BADOPT: unknown or ambiguous options (-sv).though it looks like I have the correct version (IUS 5.6)apollo stanzani:coyote > ncvlog -versionTOOL: ncvlog 05.10-s017Isn't it?Cheers
Hello Marco,You are running the LDV5.1 version of the simulator. You will need to load a later release to get access to SystemVerilog constructs. We started supporting SystemVerilog in IUS5.3, but I suggest you move to at least version IUS5.6 to get the latest supported features.Kathleen Meade
| apollo stanzani:coyote > ncvlog -version| TOOL: ncvlog 05.10-s017The version reported is five dot one, not five dot ten which it looks like. The "s017" denotes the incremental release of that version based on bug fixes, etc. that have been applied. Since the release is quite old, there have been quite a large number of releases.The latest version available is IUS57-s001. This has quite a bit of SV support in it, so you'll want to be sure to read the SystemVerilog: What's New reference.You can download the latest version from http://download.cadence.com.Tim
Hello TimI've just upgraded to 5.6 and everything works fineMany thanks for your quick and great support: now it's my problem to take advantage of system verilog properlyCheers
Hi Marco,Cadence has also been developing a SystemVerilog testbench methodology, called the "Universal Reuse Methodology" (uRM), as part of the complete Incisive Plan to Closure Methodology development effort. The methodology includes documentation, and code examples. If you can send me an email (firstname.lastname@example.org), I can put you in touch with an AE who can show you how to leverage the uRM methodology. This should make it much easier for you to come up to speed on how to use SystemVerilog for building testbenches. It also includes examples on how to connect SystemVerilog verfication components to e verification components.Regards,Mike