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Is there a way to call VHDL procedures in a SV TB without translating them into SV tasks.. ?
Hi Mirzani.Hierarchical references to VHDL are not supported yet. I believe this is due to restrictions in the VHDL specification.I've been told this will change in the next version of VHDL, but I don't know any more than that.Steve.
I should have used the word 'import' instead of call .I was wondering if there is an equivalent hdl_task(VERA) to import the VHDL procedures placed in a separate package..
Though not in LRM, in principle SV DPI can be extended for this. But why wait? I've been doing this for several years now with little WA. Pseudo-code:VHDL=======procedure vhdl_proc;...entity dummy (call_vhdl_proc : in bit)...arch.. process (call_vhdl_proc) vhdl_procVerilog--------// Instantiate the dummy VHDL, toggle the "call_vhdl_proc" HTHAjeetha, CVCwww.noveldv.com
Hi, I would also like to know if there is a way to map verilog tasks to system verilog tasks. Trying to build sys verilog wrappers around verilog tasks
Hi, Thanks for the reply. We'll be having a verification environment which includes basic verilog tasks. The upper level sys verilog TB will have to make use of these tasks. So how can I refer to these verilog tasks from sys verilog. Does importing help? or shud we wrap the verilog tasks & use something similar to hdl_task as in Vera??
Yes Same problem I am facing. I need to call [b] Verilog tasks defined in a module <> hierarchy [/b], from my [b] classes in SystemVerilog [/b]. How can it be made possible ??even defining them as extern task<> in SystemVerilog, it's giving compile time error, saying no module defined.Is there any way to call them through Interface definition etc..??RegardsMayank
Yes Same problem I am facing. I need to call Verilog tasks defined in a module <> hierarchy , from my classes in SystemVerilog . How can it be made possible ??even defining them as extern task<> in SystemVerilog, it's giving compile time error, saying no module defined.Is there any way to call them through Interface definition etc..??RegardsMayank
Mayank, To call a task from within a class, one can go via virtual interface: interface my_if; task my_task; // class my_c; virtual my_if my_if_0; task call_task(); my_if_0.my_task;However I've seen tools not fully supporting this yet/premamture support. Till then you are better off with a WA like: interface my_if;
task my_task; endtask
always @my_trigger begin my_task; endThen trigger this "my_trigger" from within the class.This was skeleton code, if you have more problems, show us full code or send it to me via email (ajeetha <> gmail), I will see if I can help.HTHAjeetha, CVCwww.noveldv.com
HI Ajeetha, I'll be calling verilog tasks from SV classes. We'll be using VCS for simulations. Do u think this would support what u've suggested in the 1st step (reply to Mayank ). or shud i go for the trigger method?In the example you have shown, interface & class are SV Files or should the interface be some header/include file. And should the always block be running in the back ground all the time?is my_trigger some kind of clock or ??ThanksDeepa
DM,I don't knew, whether you have tried this or no, but you can go down to the hierarchy, to the module, from which the task is to be called, and map it at the top.Like:**************** Code Snippet ***************`define DUT top.i_module1module top();// your TB description// To invoke the task in module1initial begin 'DUT.task-name; // "task-name" is the name of the task defined in module-1 ...end// module instantiationmod-name module1 ( //port mapping );******************************************************************This should work.- Vivek