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I have declared a data member as reg.
when i use it in an assign statement, I am supposed to get an error.Now
1. If i use the +sv switch i am not getting an error.
2. its showing an error if i do not use the +sv switch,which is as expected.
I am using cadence IUS58, please clarify on this.
Hi Manmohan,If the data member is used on transaction layer, please declear it as bit (0/1) or logic (0/1/x/z).Best regards,Davy
Hi Davy,I have used the declaration inside a modulemodule test();reg a,b;assign a = b ? 1 : 0 ;endmodulein this code with +sv command line option its not giving me an error.
In SystemVerilog, such code is now legal. Here's a snippet from the LRM:SystemVerilog extends the functionality of variables by allowing them to be either written by procedural statements ordriven by a single continuous assignment, similar to a wire.A wire can have multiple continuous assignments, like drivers on a bus. A reg can only have a single continuous assignment.
Hi TAM,thanks a lot for the reply. my doubt is now clear even though i have not checked the LRM but your commentsare sufficient. thanks & regardsManmohan Singh