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Hi thereI am starting System Verilog now and I am looking for the best practice for designing a System verilog interface for the HD Audio bus as define by Section 5 of ftp://download.intel.com/standards/hdaudio/pdf/HDAudio_03.pdfThis bus requires a master controller generating the clock, the reset and the frame sync, which drives up to 16 codec (slaves) getting the clock, the reset and the sync. I am wondering about the best way of using interfaces capabilities as mod ports and parameters to define a suitable intercae.I am starting with thisinterface hda_if (); logic rstn; logic [15:0] sdi; logic sdo; // bussed serial data output(s) logic bclk; // link 24.00-MHz clock logic sync; // 48 khz frame sync and outbound tag signal modport master (output rstn, output sync, output bclk, output sdo, inout sdi); modport slave (input rstn, input sync, input bclk, input sdo, inout sdi); task init (); begin rstn = 0; sdo = 0; @(posedge bclk); end endtaskendinterface- is it OK to define just sdi in the slave modport ( a slave codec exposes just one SDI, while the master controller handles up to 16 SDI)? What about the other, unused sdi's?- should I define the clock as an interface port - e.g. interface hda_if (input blck); I see this is done in the SPI example of the System verilog traing, still I wonder how it works for master and slave flavours. The general question is how to handle clocks in interfaces for a master/slave bus: I probably don get the point of declaring interface ports .... SHould I use this stile and use modports - what do you recommend about clock generation? Since he master is in charge to genreate bclk I wonder if it is preferred to add a clockgen in the interface decalration or in the master controller module only? e.g. default clocking bck_cb @(posedge bclk); default input #1 output #3; input sdi; output sdi; output sdo; output sync; endclocking- The clockgen generates an istance right? So I suppose it is not receommended to include in the interface (I would inclued the interface declaration in a verilog file .vh included in a number of files using the i/f). do you recommend to put the interface in a compiled packege instead?Sorry for this long email: I am eager to start with the right pace the project also fro a SW engineering standpoinAny suggestion to fix/improve my approach is really welcome