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HiWe are using IUS 6.1 and URM for VIP development.Can i go for code coverage of the complete environment that i have developed?HOw do i do that?RegardsRishi
Hi Rishi.You can do coverage of your verification environment as well as any DUT, because if you don't specify the -covdut option, the top-level is taken as the DUT for coverage purposes.The simplest set of switches would be:[i]irun -cov58 -coverage ALL[/i]Then to analyse:[i]iccr -cov58 -gui[/i]The best thing though would be for you to read the ICC tutorial which will give you a good introduction to doing coverage in IUS.You can find that under "cdsdoc", or if you prefer to use PDF docs (like me) then this will get you there:[i]acroread `ncroot`/doc/incovtut/incovtut.pdf [/i]
Steve,Can i exclude any modules, so that they are not included in coverage report? If yes, how do i do that?-Vivek.
Hi Vivek.Have a look in the ICC User's Guide (`ncroot`/doc/iccug/iccug.pdf) at the chapter "Generating Coverage Data".Specifically the -covfile option to ncelab. You start to need to use a coverage control file, which would contain something like:// cov_options.ccfselect_coverage -be -module *deselect_coverage -be -module freddeselect_coverage -be -instance top.jim.dummy// end of fileThis example would enable block and expression coverage in every module except "fred", and instance "top.jim.dummy".You can get quite creative with this is you need to, and you really should read the user guide to get an understanding of what you're doing with these commands :-)If you're using 3-step compilation (ncvlog;ncelab;ncsim) then this .ccf file is used like "ncelab -cov58 -covfile cov_options.ccf".If you're using single step (ncverilog or irun) then use "irun -cov58 -covfile cov_options.ccf".In fact, use irun, it's brilliant because it can sort out all your C, VHDL, Verilog etc files from one command line!Steve.
does anyone has idea about "ntcnotchk: option in ncsim
In the future, it would be better to start a new topic when asking a different question. This is also unrelated to SV and should go in the Simulation forum.
Now for the answer which I'm copying directly from the NC-Verilog Simulator Help docs.
Generate negative timing check (NTC) delays, but do not execute timing checks.
You can use the -notimingchecks option to turn off all timing checks in your design. However, if you have negative timing checks in the design, this option also disables the generation of delayed internal signals, and you may get wrong simulation results if the design requires these delayed signals to function correctly. That is, if you have negative timing checks, simulation results may be different with -notimingchecks and without -notimingchecks.
Use the -ntcnotchks option instead of the -notimingchecks option if you want the delayed signals to be generated but want to turn off timing checks. This option removes the timing checks from the simulation after the NTC delays have been generated.
If you are running the simulator in single-step mode with the ncverilog command, use the +ncntcnotchks option.