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How to calculate Code Coverage for a System Verilog Verification Environment?At present, i am not using a DUT. I am taking two instances of my Verfn. Environment for verification.I am able to generate functional coverage data but for code coverage how should i proceed??Can i have a specific flow to generate and calculate code coverage for the Environment w/o DUT.RegardsJagvin
Do you have a class based TB or module based? If it is module based, I would imagine ncelab -coverage would work. If it is class based then I don't believe Code Coverage is the right technique for it - though I do see a value for it in driver/checker/monitor. Perhaps tools require additional support to do that.CheersAjeetha, CVCwww.noveldv.com
Hi Jagvin.Can you see if this thread answers your question?http://www.cdnusers.org/Forums/tabid/52/forumid/66/postid/4642/view/topic/Default.aspxIf not, maybe you can be a bit more specific about what you're trying to do.Normally you can treat the TB as the "DUT" for coverage purposes, so you can do code coverage for static structures like modules.Steve.
Hi Ajeetha,I have a module based environment. I have tried few steps given in NCSIM user guide and ICCR guide for code coverage.But still, i am unable to generate cov_work directory and the files for code coverage.Can u please let me know which steps i shold take for this. I mean i have a "top", so to calculate its code coverage should i proceed with (1) Compilation (2) Elaboration (3) Simulation What different commands i can use to create cov_work and code coverage files.ThanxRegardsJagvinder
Hi Ajeetha & Steve,Thanks a lot.The command "ncelan -coverage " worked.Actually i had to use -cov58 as i am using IUS 6.1.I used the command "ncelab -cov58 -coverage all " and it created coverage database for all the coverages after simulation.Thanx once again.RegardsJagvinder