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Hi there,For some system modeling I am looking into using ncvlog in SystemVerilog mode (ncvlog -sv) since I understand from some online documentation (http://www.deepchip.com/items/0466-04.html) that in SystemVerilog real data types can be passed hierarchically through ports.Here is my test code: module test(input real x); endmodulewith the following result: ncvlog -sv test.v ncvlog: 06.11-s004: (c) Copyright 1995-2007 Cadence Design Systems, Inc. module test(input real x); | ncvlog: *E,SVNTRL (test.v,1|23): A module port that is a net cannot be of type 'real' by SystemVerilog language rules.My questions are:- does ncvlog -sv support real port types?- are real port types indeed allowed in SystemVerilog by standard?I am aware of the regular "workaround" using 64-bit vectors and $realtobits etc. but I was hoping to be able to use something more convenient.ThanksAxel
Try using the keyword 'var' in the port list// ncverilog real_io.sv +sv +linedebug +gui &module top();real rrr;one U1(rrr);two U2(rrr);endmodulemodule one(input var real rrr);initial #0 $display("%m %f", rrr);endmodulemodule two (output real rrr);initial rrr = 3.14159;endmodule
Indeed that does the trick.Thanks very much - it was hard to find this information otherwise.