Hi everyone,Most people have probably seen the announcement that came out this week on the new, open-source, Open Verification Methodology (OVM) sponsored by both Cadence and Mentor. You can check out the press release for more information. There is also an EETimes article on OVM that is worth reading.Discussion is already brewing on OVM so here is your chance to take the podium:- OVM: Hot or hype?- What challenges that you are currently facing will be facilitated by an open verification methodology?- Will OVM be a catalyst for the adoption of SystemVerilog? Why [not]?- What are you hoping to see become part of OVM?Let's hear it!-Stelix.
BTW, make sure to also check the mirror discussion on OVM in the SystemVerilog forum: http://www.cdnusers.org/Forums/tabid/52/forumid/66/postid/5127/view/topic/Default.aspx
I would like to see the OVM first before commenting or trying to answer these. Till the time we see a downloadable stuff such as AVM or a published text such as VMM it is pretty hard to comment. One thing for sure I hope is that it will run on all 3 major tools. IMHO so far the existing methodologies have not done too well on true interoperability front. Especially given that CDN is also on the bandwagon now, we would hope to see truly interoperable testbenches.If there is any industry consortium of sorts to drive towards it, I would be glad to participate from CVC side.ThanksAjeetha, CVCwww.noveldv.com
I agree with Ajeetha that we should have some detailed document regarding OVM.Other verification methodologies such as AVM and VMM are available as downloadable content which makes it to be accessible to most of the verification engineers.We should have such a stuff for OVM so that we have valuable feedback on this methodology from vast pool of engineers.