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Hi.I'm currently studying a solution to dynamically generate an e file with probes and checkers related to the actual configuration of my design.Do you know if there is a way to access the design hierarchy from either ncsim or specman? I need the same kind of information displayed in the design browser but in a more textual (and possibly parsable) form. Something like::my_top_IP:my_top_IP.compA_0:my_top_IP.compA_1:my_top_IP.compB_0.compC_0...Thank you for any suggestion.Nico
Nico, Specman has a reflect facility (RF) that can dynamically parse the Specman struct/unit hieararchy and generate a meta data file. However, I'm not aware of any such facility in Verilog.
Apart from writing your own Verilog parser, one approach might be to decompile the verilog code into a single netlist (using ncdc) and then run a script over it to generate the data that you want.
Niconcvlog's tcl interface has a command called "find". You may be able to use it to get information about design hierarchy. Nitin
Nico, NCSIM has a nice TCL interface that lets you do this easily. A combination of "scope -set" and "scope -describe/-show" plus some TCL coding should do what you want.HTHAjeetha, CVCwww.noveldv.com