Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I am currently using lp_clock_gating_control_point set to postcontrol, simply because this was set in the the scripts I inherited.
Are there any signficant advantages of postcontrol over precontrol?
I guess that postcontrol has a slight timing advantage, since precontrol has an additonal gate in the EN-D path.
Anything else? Which option do other users prefer or use?
timing is certainly a difference but I believe the biggest difference is observabiliy for DFT coverage purposes. Post control limits your ability to check proper operation of the CG latch if not mistaken
I suggest you check your target standard cell library to determine what kind of clock gating cells are available. In many cases only one type is available. For example:
$ grep clock_gating slow.lib clock_gating_integrated_cell : "latch_posedge"; clock_gating_integrated_cell : "latch_posedge"; clock_gating_integrated_cell : "latch_posedge_precontrol"; clock_gating_integrated_cell : "latch_posedge_precontrol"; In this case, you would want to use precontrol. If you chose post-control RC would be forced to build the clock gating cell from primitive components, which is obviously not what you would want.
In reply to bmiller:
Brad, the library I am using contains both pre and post control integrated cells, so this is not an issue I need to consider.
Grasshopper, I am not sure I understand your comment. I guess you mean that we will catch failts on the D input of the latch?
Thanks for the feedback,