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I am synthesizing a top level digital block that has interfaces to external pads and to a top level analog block.
When I run DFT checks, it assumes that all ports are controllable, which is not the case for the signals from the top level analog block.
Is the an attribute I can apply to these ports to indicate that they are not controllable?
In reply to grasshopper:
Excellent - this is just what I'm looking for.
Thanks for the quick feedback, Steven
Having checked further, this is not what I want. This attribute only applies to pins, and is intended for internal black boxes.
I need something to apply to design ports, and to indicate that a pin is not controllable (even though it is a primary input)
Any additonal suggestions?
In reply to moogyd:
I think the only thing you can do is prevent RC from automatically identifying test clocks and test mode signals.
To turn off auto identifcation of test signals:
set_attr dft_identify_test_signals false /
set_attr dft_identify_top_level_test_clocks false /
The defaults are "true".
You will have to manually define test clocks and test mode signals (define_dft test_clock, define_dft test_mode, etc) on the ports that CAN be controlled on the tester. Any internal clocks that cannot be controlled can have the test clock muxed on them using fix_dft_violations.
Did you get any solution for your trouble?
I have a trouble that it seems very close to your.
I need to include DFT accessibility in design but I will not have access for both input and output ports of digital circuit because they are connected to analog peripherals blocks.
Is there any command in Encouter Test or RTL Compiler which won't take in account the use of the I/O ports for the test pattern generation? I think it isn't a recommend approach for test, but in my case I need to try it.
In reply to Douglas Foster:
I did not find a solution other than to disable auto-identification as described by Brad.