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Hi, I have now seen this issue with two different designs and have not been able to figure out the root cause for this behaviour.
I have synthesized a design using RTL Compiler and have generated both mapped and an optimized netlist.
1. When I compare the RTL to mapped netlist (non-hierarchical comparison), I don't see any non-equivalent points.
2. When I compare the mapped netlist to the final optimized netlist, I don't see any non-equivalent points.
3. But when I compare RTL to final optimized netlist, I get non-equivalent points.
Looking into this matter in detail, I noticed that these non-equivalent points start showing up as soon as I run the first incremental synthesis on the mapped netlist.
Any ideas as to why the RTL to final netlist comparison are showing non-equivalencies?
I have seen this happen before too, and in my case it was caused by sequential merging in RTL-Compiler. The two step LEC flow helps LEC resolve and verify sequential merging. The single step verification flow can often resolve sequential merging, but sometimes it cannot.
The two step LEC flow is the recommended way to verify RC netlists. I suggest you continue to use the two step flow. It is the best way to prevent false-noneqs and aborts.
In reply to bmiller:
Thanks for your input on the matter.
As far as the RTL to mapped netlist comparison is concerned, should that be hierarchical or would a non-hierarchical comparison suffice?
In reply to hnfq:
Whenever RTL is the "golden" design in LEC, you should use a hierarchical compare. This will be the most efficient, and give the best chance of a successful compare with no aborts.
Also, this is the default when using write_do_lec. If RTL is the golden, write_do_lec will write out a hierarchical compare script, unless you explicitly say -flat. Similarly, if you are generating a dofile with write_do_lec and you specify a -golden netlist (such as in the intermediate-to-final comparison), write_do_lec will default to writing a flat compare script.
Is there a reason why you would prefer a flat compare with RTL as the golden?
No, there wasn't any particular reason for running flat comparison. I just wanted to make sure that whether I run hierarchical or flat comparison I would be able to rely on the final result.
Appreciate your input on this issue. Thanks.
You can certainly rely on the final result whether you run flat or hierarchical.
If you'd like to have the option to run both ways, I suggest writing out two LEC dofiles with the write_do_lec command; one with -flat, and one without.
But, the preferred method is to run hierarchical if RTL is golden.
Can you explain what does sequential merging and sequential constanting mean?
In reply to Manoj Kumar S:
Sure. Sequential merging is when the synthesis tool merges two or more flops into one because they have the exact same function. Sequential constant is when the synthesis tool optimizes away flops that are always tied to 1'b1 or 1'b0.
Thank, I had the same Mismatch and your posts helped me also I found more Cdence blog.
In reply to r u verified:
unfortunately you do not include enough information for anyone to help you. You should include the schematic showing the nonEQ. You indicate LEC is confuse. Can you shed light why you think LEC is confused and the nonEQ is not real? Better yet, if the circuit is simple as you indicate, I believe the schematic should help you understand the difference and whether it is a real issue, setup issue, or something else.
hope this helps,