Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I want to get a quick look at the power consumption of one block.
--use RTL Compiler generate netlist(after syn) and sdf
--run gate sim with or without sdf annotated, get VCD
--use netlist and VCD in ETS, get power consumption
I found the power consumption get form VCD without sdf annotated is much greater than with sdf annotated.
This makes me confuse. I think the power with sdf annotated should be bigger. Can anyone help to explain this?
I found there is only one difference with the log (the value changes got from vcd).
without sdf annotated:
With this vcd command, 12005021 value changes and 1e-06 secondsimulation time were counted for power consumption calculation.
Filename (activity) :../in/ad9651_datapath_top_gate.vcd Names in file that matched to design : 234754/352833 Annotation coverage for this file : 54305/54305 = 100%
Activity annotation summary: Primary Inputs : 89/89 = 100% Flop outputs : 8172/8172 = 100% Memory/Macro outputs : 0/0 = 0% Tristate outputs : 0/0 = 0% Total Nets : 54305/54305 = 100%
with sdf annotated:
With this vcd command, 6867391 value changes and 1e-06 secondsimulation time were counted for power consumption calculation.
not sure what you are trying to compare. Is it
gates + activity(RC) vs. gates + SDF + activity(ETS) ?
The first thing I notice is that your annotation is different yet you are using the same netlist. The SDF should not affect your toggle annotation as far as I can tell hence I would focus on understandig that first. Obviously until your annotation lines up, the rest of the numbers do not have much of a chance. Same netlist and same activity information should produce the same annotation regardless of tools or additional files read. Then start peeling the onion on power numbers
In reply to grasshopper:
Thanks for your reply.
What I want to compare is
netlist(after syn) + gate_VCD(without sdf annotation) VS netlist(after syn) + gate_VCD(with sdf annotation).
The power analysis tool is ETS for both. The sdf is generated after syn. The netlist is the same.
In your reply you said you noticed the annotation is different yet I used the same netlist, do you mean "12005021 value changes" and "6867391 value changes "? That's what confused me. I don't know how the ETS get value changes from VCD, but I think the VCD with sdf annotation shoud have more transitions(the combitional cells would toggle more for it's inputs have different delay).