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I have a generate statement in my verilog RTL.
generate for(g=0; g<num_reg; g=g+1) begin
wb_reg #(._address(reg_addr[g*_width+:_width]), ._default(reg_default[g*_width+:_width]), ._bit_mask(reg_bit_mask[g*_width+:_width]), ._autoclr(reg_autoclr[g*_width+:_width])) wb_regs ( .CLK_I(CLK_I), .RST_N_I(RST_N_I), .TEST_EN_I(TEST_EN_I), .ADR_I(SADR_I), .DAT_I(SDAT_I), .DAT_O(dat_o[g]), .ACK_O(ack_o[g]), .CYC_I(SCYC_I), .STB_I(SSTB_I), .WE_I(SWE_I), .REG_SEL_O(reg_sel_o[g]), .REG_DATA_O(reg_data_o[g]), .REG_DATA_I(ro_data[g*_width+:_width]), .REG_UPDATE_I(reg_update_i[g])); end endgenerate
After synthesizing with RC 8.1, the netlist generated for this block has following naming style.
Same naming sytle is in SDF file generated for this design using
write_sdf -design foo -version "OVI 3.0" -delimiter "/" >
The problem is "." before wb_regs is causing syntax issue when running simulation using SDF file. The error is
ncsdfc: *E,SDFIRE: "../../../synthesis/foo/outputs/foo_netlist.sdf", line 50115: Syntax error ".".ncelab: *W,SDFCNC: Cannot compile SDF file, ../../../synthesis/foo/outputs/foo_netlist.sdf - skipping annotation.
I have tried
set_attribute hdl_array_naming_style "%s_%d"set_attribute hdl_array_generator "%s_%d"set_attribute hdl_reg_naming_style "%s_reg%s"
in synthesis scripts but none of these fix the problems.
Is there a certain attribute related to module generate naming style that may fix the problem. Pls suggest.
Thanks for your time.
in RC91 you can use the following
attribute name: hdl_generate_index_style category: elab (controls elaboration) object type: root access type: read-write data type: string default value: %s[%d] help: Format of 'for generate' block labels. attribute name: hdl_generate_separator category: elab (controls elaboration) object type: root access type: read-write data type: string default value: . help: String used to separate generate block labels.
I am not sure if RC81 also had these
In reply to grasshopper:
Thanks gh. I appreciate your help. It worked after using those two attributes.
Three other attributesare used to control the naming style for generate statements in RC
# Specifies whether 'if' generate labels should be used to prefix instances, default true, allowed [ true | false ]
set_attr hdl_use_if_generate_prefix false /
# Specifies whether 'for' generate labels should be used to create instance names, default true, allowed [ true | false ]
set_attr hdl_use_for_generate_prefix false /
# String used to separate generate block labels, default "."
set_attr hdl_generate_separator "" /
In reply to mclarke:
Thanks mclarke, this is even more helpful.
In reply to diablo:
Badly needed this2 attributes, glad to find it here..thanks