Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I have a RTL which after synthesis looks as in the snippet mentioned below..
wire [2:0] seed_inp; wire [2:0] seed_outp;
wire scan_5_q, scan_9_q, scan_10_n_0, scan_10_q, scan_11_n_0, scan_11_q, scan_12_n_0, scan_12_q; wire scan_fix0_6_n_0, scan_fix0_6_n_1, scan_fix0_6_q, scan_fix0_8_n_6, scan_fix0_8_n_8, scan_fix0_8_n_14, scan_fix1_2_n_0, scan_fix1_2_q; df1qpdw scan_10_q_reg(.CP (clk), .D (scan_10_n_0), .Q (scan_10_q)); mx21x2pdw scan_10_g22(.D0 (seed_inp), .D1 (scan_10_q), .S0 (scan), .Z (scan_10_n_0));
I wanted RTL compiler to take the above sinppet as
df1qpd scan_8_q_reg(.CP (clk), .D (seed_outp), .Q (scan_8_q));
mx21x2pd scan_8_g20(.D0 (seed_inp), .D1 (scan_8_q), .S0 (scan), .Z (seed_outp));
Functionality wise both are same but I am getting unnconnected in the netlist because of this issue..
wire [2:0] seed_inp; wire [2:0] seed_outp;
Is as written in the RTL and scan_9* scan_10* etc are as written out by RTL compiler after synthesis.
Is there a way I can force the RTL compiler not to use its own wire names but to retain the wire names as written in RTL ?
I believe you are looking for this
attribute name: write_vlog_preserve_net_name category: write (controls write output) object type: root access type: read-write data type: boolean default value: false help: Determines whether to preserve net names present in user input or not.
Note that dangling wires resulting in incorrectly implemented functionality would be a bug in the tool. Did you run LEC ? I suspect if the wire became unconnected it probably could be optimized out but obviously I have no knowledge of RTL or functionality
In reply to grasshopper:
I could not find that command in the manual. But some how that also did not help. May be I will try different version of RTL compiler and check.
The signal was getting optimized out. I have one generic question to you. How does these unconnected or optimised nets gets handled
during PNR. I mean if the gate levels has few ports as "unconnected" how does this gets sorted out during further stages, will it be tied off?