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I am traying to synthesize a design to a library with no basic inverters. In general, RTL compiler requires inverters and some other basic cells. and so i will recieve : "synthesis failed- do not have usable inverters".
My library have all the logical veriaty of cells except a straight forward inverter. meaning, including: (A+B'), AB', A(BC)'...... and alot more options to create an inverter out of them.. or to combine it with the approximate cells for one of the above functions .
There-for, from the aspect of logical veriaty the synthesizer can deal with no specific inverters. Can I some-how delete this requirement of implicitly have an inverter cell ? or am i some-how hitting on some heuristics that suddenly are invalid with the absence of the inverter??
Thank you very much