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While using RTL compiler I get the following warning message. [CDFG-420]
Trimmed index 'portIn' of signal 'startT0' from 2 bits to 1 bits in file
The code for above is :
parameter PORTS = 4;
input wire [1:0] portIn;
input wire [3:0] cntIn;
reg [PORTS -1:0] pauseDa;
0: pauseDa[portIn] <= x;
I noticed that in other instances, when I used an integer instead of a binary number, it gave the same warning.
As soon as I converted 0 to 1'b0 and 1 to 1'b1, this warning was not issued any more.
In the above case, whenever, a bus was used as the index, it issues the above warning. From the code above, we
know pauseDa can have 4 values and portIn can address 4 locations. But the warning says trimming index to 1 bit.
There was no such problem when integers were used for indexing. (in a for loop). So, I modified the code as follows,
assign portIn_int = portIn;
0: pauseDa[portIn_int] <= x;
But I continue to get the same warning.
Trimmed index 'portIn_int' of signal 'pauseDa' from 32 bits to 2 bits
The problem is even though the RTL and netlist can be verified each time using verplex, I have to still go through the
logs to make sure that all these warnings are ok.
Alternatively, I could set:
set_attr hdl_trim_target_index false
but it mentions that the design is not optimized. I did verify, that there is a slight increase in area with the above
setting to false. Default is true.
Any suggestions or similar experiances are appreciated.
Sorry, I put the wrong Warning number. The correct one is : [CDFG2G-617]Thanks,Amar
just tried the following code:
module debug (
input wire [1:0] portIn,
input wire [3:0] cntIn, in1,
output wire [3:0] out1
parameter PORTS = 4;
reg [PORTS -1:0] pauseDa;
// wire integer portIn_int;
// assign portIn_int = portIn;
always @(cntIn or portIn or in1) begin
0: pauseDa[portIn] <= in1;
endcase // case(cntIn)
end // always @ (cntIn)
assign out1 = pauseDa;
endmodule // debug
and I can see the CDFG2G-617 when I do the mod you did. In that case, it makes sense to me since integers are 32 bits and pauseDa is 2 hence the tool has to trim or else you could give up some optimizations. I noticed that your thread talks about another signal for which you do not show the code
> Trimmed index 'portIn' of signal 'startT0' from 2 bits to 1 bits in file
It probably is a similar issue. If you can share the code with startT0 I can probably help you out.
I am using 6.2-s010, what version are you using ?