Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
While using RTL compiler I get the following warning message. [CDFG-420]
Trimmed index 'portIn' of signal 'startT0' from 2 bits to 1 bits in file
The code for above is :
parameter PORTS = 4;
input wire [1:0] portIn;
input wire [3:0] cntIn;
reg [PORTS -1:0] pauseDa;
0: pauseDa[portIn] <= x;
I noticed that in other instances, when I used an integer instead of a binary number, it gave the same warning.
As soon as I converted 0 to 1'b0 and 1 to 1'b1, this warning was not issued any more.
In the above case, whenever, a bus was used as the index, it issues the above warning. From the code above, we
know pauseDa can have 4 values and portIn can address 4 locations. But the warning says trimming index to 1 bit.
There was no such problem when integers were used for indexing. (in a for loop). So, I modified the code as follows,
assign portIn_int = portIn;
0: pauseDa[portIn_int] <= x;
But I continue to get the same warning.
Trimmed index 'portIn_int' of signal 'pauseDa' from 32 bits to 2 bits
The problem is even though the RTL and netlist can be verified each time using verplex, I have to still go through the
logs to make sure that all these warnings are ok.
Alternatively, I could set:
set_attr hdl_trim_target_index false
but it mentions that the design is not optimized. I did verify, that there is a slight increase in area with the above
setting to false. Default is true.
Any suggestions or similar experiances are appreciated.
Sorry, I put the wrong Warning number. The correct one is : [CDFG2G-617]Thanks,Amar
just tried the following code:
module debug (
input wire [1:0] portIn,
input wire [3:0] cntIn, in1,
output wire [3:0] out1
parameter PORTS = 4;
reg [PORTS -1:0] pauseDa;
// wire integer portIn_int;
// assign portIn_int = portIn;
always @(cntIn or portIn or in1) begin
0: pauseDa[portIn] <= in1;
endcase // case(cntIn)
end // always @ (cntIn)
assign out1 = pauseDa;
endmodule // debug
and I can see the CDFG2G-617 when I do the mod you did. In that case, it makes sense to me since integers are 32 bits and pauseDa is 2 hence the tool has to trim or else you could give up some optimizations. I noticed that your thread talks about another signal for which you do not show the code
> Trimmed index 'portIn' of signal 'startT0' from 2 bits to 1 bits in file
It probably is a similar issue. If you can share the code with startT0 I can probably help you out.
I am using 6.2-s010, what version are you using ?