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Here I want to address an issue, which in my idea can be easily problematic for people who are trying to do any kind of logic simulation of their design during synthesis.
you can write back the produced netlist as a verilog file for logic simulation:
write_hdl -generic > design/top_generic.v
my default assumption was that, the generated verilog file does not contain any delay values inside and it is reflecting the operation of the circuit at the current synthesis stage however, this assumption is wrong!!!
in the flip-flop model used inside the file there is #1 delay.
putting this delay is reasonable, since you want to show that things are happening after clock edge.
But it can be very easily problematic especially for designs that are working in the range of 1GHz frequency.
solution is either to
- carefully selecting 'timescale value (eg. 1ps/1ps)
- edit the file and put a very small delay value instead of this big delay !!! (e.g. 0.001 if timescale is 1ns/1ps)
please let me know if this is correct? or there is any other solution....