Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Hello Everybody,I thought I would shared a recent experiece I had which will show you another side of FEV.During my last project we kept running in paths not being properly disable during test mode (clock mux not propagating the right clock or propagating multiple clocks, clock gating not being turned off, bypass inactive) and some similar issues. Now we are in 65nm and using a custom library so we thought we had some modeling issues and spent a long time reviewing cells modeling without finding anything explaining the issues we were having. After discussing with the engineer in charge of our top level FEV, he mentioned that we were clean and only had a few inverted equivalent which he verified and were fine. Here I asked him to provide me the list so I can try to understand why the synthesis too was doing that when I was not expecting it (turn out it was an option in DC ). Also while reviewing the list I noticed that a few of the FF in our test controller were inverted equivalent and BINGO!!! Here goes the problem. Sure enough after the STA engineer, inverted the case_analysis our STA started to make sense. Here is what we learned out of this: - Have better documentation (bit hallway discussion and email exchange any day) - Keep current with FEV status and inverted equivalent FF to check that important FF in your design are not impacted. The weirdest thing during the whole time was that the ATPG gate level sims keep passing and we could not explain why....I hope this will help somebody else and if not that you enjoyed the story.Thanks,Eric.
Hi Eric and all,I have a related question here.Some FFs are status FF, like test-modes etc. Sometime we have to put a set-case-analysis on the output of those FFs. However, after synthesis, sometime the Q-Bar output is used, and thus the SDC is broken. Is there a way to ask the synthesis tool not to do this (i.e. use Q, and not Q-Bar) for some selected reg?Regards,Eng Han
Hi Eng,sorry for not responding earlier but I missed your post.I believe there is a way to specify which FFs a given register can mapped to but often in practice this is very hard to manage and most likely synthesis tool dependant. If you tell me which tool you are using I can try to find out.Best solution is to instantiate the FF you want directly in your RTL (using a intermediate level of hierarchy so you can have either the gate or some rtl for simulation and other analysis purposes) and to put a size_only or dont_touch attribute on those FFs.Regards,Eric.