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Hi fellow members!
i need help on the topic of forward body biasing.
I am currently using the 65nm process with a wp/wn ratio of 240/120 which is 2.
In regards to the body of the pmos and nmos, i normally tie them to VDD
and GND respectively. However, coming upon the topic of forward body
biasing i am quite confused as to how should i implement the technique?
Could anyone help me out? Thanks! :) i realize in some circuits, simply apply a "0" to the pmos body and this provides FBB. Dont seem to understand why though.
Would appreciate any form of help.
Does anyone has experience with CSAFF and CHLFF circuits? need help too.. complementary sense amplifier flipflop and complementary hybrid latch flipflop.