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i have thi s query regarding RC tool, as to how will the tool be able to exclude the delay cells in a design during synthesis.
set_attr avoid true <list of cells to avoid> /
in general, I do not believe RC will use the delay cells since buffers are of similar size and better performance so not very likely to RC to pick the delay cells since it is not trying to close hold. For more information, please refer to the RC Timing Analysis document or the ample informatoin on timing analysis and SDC on the web.